1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to modeling of an IC chip relative to across reticle variation and a related reticle.
2. Background Art
In the integrated circuit (IC) chip fabrication industry, accurate modeling of across chip parametric variation is critical to producing products that function as intended. As the geometries used in technologies shrink and products use lower voltages to conserve power, across chip variation has become an increasing part of total variation and the within chip impact of particular parameters on timing (set up and hold) determines whether a product will function as intended or not. IC products timed with accurate across chip variation models will work in customer applications. Parametric variations are created across a wafer during fabrication. Model-to-hardware correlations are generated by modeling based on data from a scribe line test structure placed in a scribe line of a reticle used to form IC chips on a wafer. This modeling is referred to as across chip variation (ACV) modeling. Current modeling approaches use information from one scribe line (kerf) test structure on a reticle. For example, FIG. 1 shows a reticle (mask) 10 used to generate one or more IC chips 12A-D. Reticle 10 may include one or more copies of each IC chip 12A-D thereon, and includes one scribe line test structure 14 in an outermost scribe line 16 of reticle 10. (Reticle 10 may represent, for example, a 30 mm by 30 mm field). Structure 14 is used mostly for mask overlay alignment, but may also include circuitry for defect monitoring (e.g., via opens) and parametric measurements. Unfortunately, variation is known to exist across the exposure field of reticle 10. As a result, data is not collected on a variety of across reticle parametric variations. For example, data may not be collected across the reticle's exposure field relative to variations for channel length, width, saturation threshold voltage (Vtsat), rapid thermal anneal (RTA), delay, resistance, or scribe line print and etch variation. As a result, across reticle variation is not considered during the fabrication process and IC chip qualification at a device level. Further, across reticle variation is not measured in the manufacturing line, so consideration of the impact of process changes on across reticle variations and the provision of in-line corrections is prohibited. The first time a across reticle variation causing a failure is identified is after the finished IC chip fails a test.